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Add a revision of the ISA design
[jade-mouse] / isa.txt
1 ALU2: add sub and lsl rol or xor bic
2 ALU1: inc dec neg compl
3 ALUI: add7 sub6 lsl lsr asr rot and or xor
4
5 76543210
6 --------
7 0000aabb => MOVE: a = b # when a != b
8 0000aabb => CALL: call a # when a == b, r0 <- ret
9 0001aaoo => ALU1: a = op a
10 001faa00 0iiiiiii => LDST: a <-> [imm]
11 001faa00 1iiiiibb => LDST: a <-> [b + imm]
12 001faa10 => LDST: a <-> [r2]
13 001faabb => LDST: a <-> [b-1:b]
14 0100aabb iiiiiiii => JMPR: jump aa # when a == b
15 01010000 iiiiiiii => JMPI: jump offset
16 01010101 iiiiiiii => CALI: call offset
17 01010101 iiiiiiii => CALI: call offset
18 010oaabb oiiiiiii => BRNC: branch if a op b
19 0110aa00 0iiiiiii => ALUI: a = a + imm
20 0110aa00 10iiiiii => ALUI: a = a - imm
21 0110aa00 11oooiii => ALUI: a = a op imm
22 0110aaoo iiiiiiii => ALUI: a = a {and, or, xor} imm
23 0111aabb => SKIP: skip if a ule b
24 1oooaabb => ALU2: a = a op b
25
26
27 Encoding branch conditions:
28 We want: eq/ne, test/testn, lt/gt, ule/ugt
29 We have 2 operand bits, so we can encode eq, test, lt, ult, and get the negations by swapping operands.
30 For example, if aa < bb, then we use eq, and if bb < aa, we use ne.
31 This is natural for lt/gt, and the comparison for eq/ne etc. just needs 1 LUT4.
32
33 Load/store should use register pairs, and then specific registers numbers can encode whether it should use the larger instructions.
34
35 Skip is valuable because it lets you implement wider add/sub with a relatively short instruction sequence.
36 For instance, you can do:
37
38 a1 = a1 + b1
39 a2 = a2 + b2
40 skip if b1 ule a1
41 a2 = inc a2
42
43 to compute [a2:a1] + [b2:b1]