Refactor "end instruction"
Add simulation, make address lines combinatorial Adding a clocked memory unit exposed a timing issue in the previous implementation of the memory ports. When the core used synchronous address lines, it seemed to end up interpreting a loaded value from an LW as an instruction word.
Add basic multi-cycle core prototype This multi-cycle core is inspired by the "6800 in nMigen" YouTube series. It's currently not optimized for frequencies or really anything, except convenience of implementation. There are no tests because it's late at night and I'm sleepy. :(