From: Cassie Jones Date: Thu, 30 Jan 2020 21:03:46 +0000 (-0500) Subject: Refactor "end instruction" X-Git-Url: https://git.witchoflight.com/jade-rabbit/commitdiff_plain?ds=inline Refactor "end instruction" --- diff --git a/core.py b/core.py index fc8913a..0f2661d 100644 --- a/core.py +++ b/core.py @@ -2,6 +2,7 @@ from enum import Enum from nmigen import * from nmigen.build import Platform from nmigen.cli import main +from nmigen.hdl.ast import Statement class Op(Enum): ADD = 0b000 @@ -45,7 +46,7 @@ class JadeRabbitCore(Elaboratable): self.cycle = Signal(range(5)) self.regs = Array(Signal(32, name=f"r{i}") for i in range(8)) - def decode(self, m: Module, inst: Value) -> None: + def decode(self, m: Module, inst: Statement) -> None: reg_a, reg_b = inst[19:22], inst[16:19] m.d.sync += [ self.inst.eq(inst), @@ -60,6 +61,10 @@ class JadeRabbitCore(Elaboratable): self.b.eq(self.regs[reg_b]), ] + def end_inst(self, m: Module, dest: Statement) -> None: + m.d.sync += self.cycle.eq(0) + m.d.sync += self.pc.eq(dest) + def elaborate(self, platform: Platform) -> Module: m = Module() with m.If(~self.halted): @@ -76,14 +81,12 @@ class JadeRabbitCore(Elaboratable): with m.If(self.cycle == 2): tmp = self.a + self.b m.d.sync += self.regs[self.reg_d].eq(tmp) - m.d.sync += self.cycle.eq(0) - m.d.sync += self.pc.eq(self.pc + 1) + self.end_inst(m, self.pc + 1) with m.Case(Op.NOR): with m.If(self.cycle == 2): tmp = ~(self.a | self.b) m.d.sync += self.regs[self.reg_d].eq(tmp) - m.d.sync += self.cycle.eq(0) - m.d.sync += self.pc.eq(self.pc + 1) + self.end_inst(m, self.pc + 1) with m.Case(Op.LW): with m.If(self.cycle == 2): m.d.comb += self.en.eq(True) @@ -91,8 +94,7 @@ class JadeRabbitCore(Elaboratable): m.d.comb += self.rw.eq(Rw.READ) with m.If(self.cycle == 3): m.d.sync += self.regs[self.reg_b].eq(self.d_in) - m.d.sync += self.cycle.eq(0) - m.d.sync += self.pc.eq(self.pc + 1) + self.end_inst(m, self.pc + 1) with m.Case(Op.SW): with m.If(self.cycle == 2): m.d.comb += self.addr.eq(self.a + self.offset) @@ -100,30 +102,25 @@ class JadeRabbitCore(Elaboratable): m.d.comb += self.rw.eq(Rw.WRITE) m.d.comb += self.d_out.eq(self.b) with m.If(self.cycle == 3): - m.d.sync += self.cycle.eq(0) - m.d.sync += self.pc.eq(self.pc + 1) + self.end_inst(m, self.pc + 1) with m.Case(Op.BEQ): with m.If(self.cycle == 2): dest = self.pc + 1 + self.offset dest = Mux(self.a == self.b, dest, self.pc + 1) - m.d.sync += self.cycle.eq(0) - m.d.sync += self.pc.eq(dest) + self.end_inst(m, dest) with m.Case(Op.JALR): with m.If(self.cycle == 2): same_reg = self.reg_a == self.reg_b dest = Mux(same_reg, self.pc + 1, self.a) m.d.sync += self.regs[self.reg_b].eq(self.pc + 1) - m.d.sync += self.cycle.eq(0) - m.d.sync += self.pc.eq(dest) + self.end_inst(m, dest) with m.Case(Op.HALT): with m.If(self.cycle == 2): m.d.sync += self.halted.eq(True) - m.d.sync += self.cycle.eq(0) - m.d.sync += self.pc.eq(self.pc + 1) + self.end_inst(m, self.pc + 1) with m.Case(Op.NOOP): with m.If(self.cycle == 2): - m.d.sync += self.cycle.eq(0) - m.d.sync += self.pc.eq(self.pc + 1) + self.end_inst(m, self.pc + 1) return m def inputs(self):