From: Cassie Jones <code@witchoflight.com>
Date: Mon, 3 Feb 2020 07:27:35 +0000 (-0500)
Subject: Add the wait state to the state machine
X-Git-Url: https://git.witchoflight.com/jade-rose/commitdiff_plain?ds=inline

Add the wait state to the state machine

The implementation of the WAIT state currently constantly reads from
memory at the WAIT-ed address, resuming when a nonzero value comes back.
It might be better to have specific support for that in an interrupt
controller type of hardware which would send notifications when the
appropriate address changed.
---

diff --git a/hardware/core.py b/hardware/core.py
index 7a2fdc1..1e02cb4 100644
--- a/hardware/core.py
+++ b/hardware/core.py
@@ -7,6 +7,7 @@ class CpuState(Enum):
     EXEC = 1
     EXEC2 = 2
     HALT = 3
+    WAIT = 4
 
 
 class Core(Elaboratable):
@@ -53,6 +54,20 @@ class Core(Elaboratable):
         with m.Elif(self.state == CpuState.EXEC2):
             m.d.sync += self.state.eq(CpuState.READ)
             self.execute2(m, self.inst, self.d_in)
+        with m.Elif(self.state == CpuState.WAIT):
+            # This should be changed to avoid reading from memory every cycle
+            # for power purposes. Instead in the wait state we should just
+            # leave the address line set and the output line high, and let an
+            # external interrupt controller send back a wake signal.
+            m.d.comb += self.addr.eq(Cat(self.it, self.data1))
+            m.d.comb += self.r_en.eq(True)
+            with m.If(self.d_in):
+                m.d.sync += self.state.eq(CpuState.READ)
+                m.d.comb += [
+                    self.r_en.eq(False),
+                    self.w_en.eq(True),
+                    self.d_out.eq(self.d_in - 1),
+                ]
         return m
 
     def execute(self, m, inst):
@@ -63,12 +78,18 @@ class Core(Elaboratable):
             with m.Case("00000001"):  # NOPE
                 pass
             with m.Case("00000010"):  # PRNT
-                m.d.comb += self.debug.eq(self.it)
-                m.d.comb += self.debug_en.eq(True)
+                m.d.comb += [
+                    self.debug.eq(self.it),
+                    self.debug_en.eq(True),
+                ]
             with m.Case("00000011"):  # WAIT
-                pass  # @TODO: Implement WAIT
+                m.d.sync += self.state.eq(CpuState.WAIT)
+                m.d.comb += [
+                    self.addr.eq(Cat(self.it, self.data1),
+                    self.r_en.eq(True),
+                ]
             with m.Case("0000010-"):  # reserved
-                pass
+                m.d.sync += self.state.eq(CpuState.HALT)
             with m.Case("00000110"):  # CABA
                 pass  # @TODO: Implement CABA
             with m.Case("00000111"):  # COFA