From 15d9e4c8a21433eb27cda185f9c2d635651bf4cf Mon Sep 17 00:00:00 2001
From: Cassie Jones <code@witchoflight.com>
Date: Sat, 11 Jan 2020 00:58:12 -0500
Subject: [PATCH] Add Jordan Rose's ISA spec

---
 isa.txt | 80 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 80 insertions(+)
 create mode 100644 isa.txt

diff --git a/isa.txt b/isa.txt
new file mode 100644
index 0000000..041ecb7
--- /dev/null
+++ b/isa.txt
@@ -0,0 +1,80 @@
+ISA by Jordan Rose
+
+Eight completely symmetric general-purpose registers (r0-7)
+Special registers: pc, it (accumulator), data1 (segment), data2 (segment), code (segment)
+
+7654_3210
+
+0000_0000          TRAP (invalid)
+     0001
+     001x
+     0100          JABS jump absolute to code[it]
+     0101          CABS call absolute code[it], it <- return addr, code <- return segment
+     0110          JOFF jump pc ± it
+     0111          COFF call pc ± it, it <- return offset (-it + 1)
+
+0000_1aaa          SWAP a <- it, it <- a
+   1_0aaa          GETR it <- a
+   1_1aaa          SETR a <- it
+
+0010_0000          GET1 it <- data1
+     0001          GET2 it <- data2
+     0010          GETC it <- code
+     0011               (reserved for another special register)
+     01xx
+     1000          SET1 data1 <- it
+     1001          SET2 data2 <- it
+     1010          SETC code  <- it
+     1011               (reserved for another special register)
+     11xx
+
+0011_0ooo          ALU1 it <- {zero, lsl1, lsr1, asr1, incr, decr, comp, negt} it
+     1aaa          ISLT "is less than", for testing overflow / carries: it <- (it < a) ? 1 : 0
+01oo_oaaa          ALUR it <- it {addr, subr, andr, iorr, xorr, lslr, lsrr, asrr} a
+
+100i_0aaa          LD1U it <- data1[a], then a += i
+  0i_1aaa          ST1U it <- data1[a], then a -= i
+  1i_0aaa          LD2U it <- data2[a], then a += i
+  1i_1aaa          ST2U it <- data2[a], then a -= i
+
+110x_xxxx
+1110_xxxx
+
+1111_00oo iiiiiiii ALUI it <- it {andi, iori, xori, (see below)} i
+     0011 0iiiiiii ALUI it <- it + i (ADDI)
+     0011 100ooiii ALUI it <- it {roli, lsli, lsri, asri} i
+     0011 101xxxxx      (probably permanently unused, but you could cram in more small ALU ops?)
+     0011 11iiiiii ALUI it <- it + (whole field, thus allowing many negative numbers) (ADDI)
+     0100 iiiiiiii BEZI branch ±i if it == 0
+     0101 iiiiiiii      (reserved branch; SUB2, BLTI is no faster than ISLT, BEZI)
+     0110 iiiiiiii JOFI jump to ±i
+     0111 iiiiiiii COFI call ±i, it <- return offset (-it + 2)
+     1xxx iiiiiiii      (reserved w/ immediate)
+
+
+Some dubiously "nice" properties:
+- 0 is invalid
+- 1111_xxxx takes immediate
+- No reg/imm ops, so data line can be the immediate
+- Two data segments, because I'm generous like that
+- get/set pairs consistently differentiated by bit 5
+- jump/call pairs differentiated by bit 0
+- The nicest instruction is "ADDR r5"
+- Near and far calls (okay, this is not nice)
+
+
+# Half-adder it + r0
+ADDR r0
+SETR r1
+ISLT r0
+SWAP r1
+# main result in it, carry in r1
+# more work to make a full adder though
+
+# Half-subtractor it - r0
+SETR r1
+ISLT r0
+SWAP r1
+SUBR r0
+# main result in it, carry in r0
+# more work to make a full subtracter
-- 
2.47.0