From 73d5207f5edc0ceaca9e1af86f7690b5e39b12a5 Mon Sep 17 00:00:00 2001 From: Cassie Jones Date: Fri, 26 Apr 2019 23:02:08 -0400 Subject: [PATCH] Add README and an example verilog file --- README.md | 4 ++++ example/seg7.sv | 38 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+) create mode 100644 README.md create mode 100644 example/seg7.sv diff --git a/README.md b/README.md new file mode 100644 index 0000000..47df648 --- /dev/null +++ b/README.md @@ -0,0 +1,4 @@ +# Minecraft Logic Synthesis Project + +I had the terrible idea of synthesizing Verilog to redstone with yosys and nextpnr. +Let's figure out how to do that! diff --git a/example/seg7.sv b/example/seg7.sv new file mode 100644 index 0000000..9106a95 --- /dev/null +++ b/example/seg7.sv @@ -0,0 +1,38 @@ +module seg7(input [3:0] in, output logic [6:0] out); + +// -0- +// 5| |1 +// |-6-| +// 4| |2 +// -3- +// --- --- --- --- --- --- +// | | | | | | | | | | +// | | | --- ---| ---| --- |--- | +// | | | | | | | | | | +// --- --- --- --- --- +// --- --- --- --- --- --- +// | | | | | | | | | | | +// |---| ---| |---| |--- | ---| |--- |--- +// | | | | | | | | | | | | +// --- --- --- --- --- --- + +always @* case (in) + 4'h0: out = 7'b0111111; + 4'h1: out = 7'b0000110; + 4'h2: out = 7'b1011011; + 4'h3: out = 7'b1001111; + 4'h4: out = 7'b1100110; + 4'h5: out = 7'b1101101; + 4'h6: out = 7'b1111101; + 4'h7: out = 7'b0000111; + 4'h8: out = 7'b1111111; + 4'h9: out = 7'b1101111; + 4'hA: out = 7'b1110111; + 4'hB: out = 7'b1111100; + 4'hC: out = 7'b0111001; + 4'hD: out = 7'b1011110; + 4'hE: out = 7'b1111001; + 4'hF: out = 7'b1110001; +endcase + +endmodule -- 2.43.2