module shift_reg #(
    parameter WIDTH=1,
    parameter DEPTH=4
) (
    input clock,
    input [WIDTH-1:0] in,
    output [WIDTH-1:0] out
);

reg [WIDTH-1:0] state [DEPTH-1:0];
assign out = state[DEPTH-1];

integer i;
always @(posedge clock) begin
    state[0] <= in;
    for (i = 1; i < DEPTH; i=i+1) begin
        state[i] <= state[i-1];
    end
end

endmodule