`define FP3_PINF 3'b010
`define FP3_NINF 3'b110
`define FP3_PNAN 3'b011
`define FP3_ANAN 3'b?11
`define FP3_ANYF 3'b???

// A NaN gate! Computes `Inf - max(x+y, -Inf)`.
// See http://tom7.org/nand/
module nan_fp3(
    input      [2:0] A,
    input      [2:0] B,
    output reg [2:0] Y
);

always begin
    casez ({A, B})
    {`FP3_ANYF, `FP3_ANAN}, {`FP3_ANAN, `FP3_ANYF}: Y = `FP3_PINF;
    {`FP3_PINF, `FP3_NINF}, {`FP3_NINF, `FP3_PINF}: Y = `FP3_PINF;
    {`FP3_ANYF, `FP3_PINF}, {`FP3_PINF, `FP3_ANYF}: Y = `FP3_PNAN;
    default: Y = `FP3_PINF;
    endcase
end
endmodule

// Convert a bit into an fp3
module bit_to_fp3(input A, output [2:0] Y);
assign Y = A ? `FP3_PNAN : `FP3_PINF;
endmodule

// Convert an fp3 into a bit
module fp3_to_bit(input [2:0] A, output reg Y);
always begin
    casez (A)
    `FP3_ANAN: Y = 1'b1;
    default: Y = 1'b0;
    endcase
end
endmodule

`define FP4_PINF 4'b0100
`define FP4_NINF 4'b1100
`define FP4_PNAN 4'b0111
`define FP4_1NAN 4'b?101
`define FP4_2NAN 4'b?11?
`define FP4_ANYF 4'b????

module nan_fp4(
    input      [3:0] A,
    input      [3:0] B,
    output reg [3:0] Y
);

always begin
    casez ({A, B})
    {`FP4_ANYF, `FP4_1NAN}, {`FP4_1NAN, `FP4_ANYF}: Y = `FP4_PINF;
    {`FP4_ANYF, `FP4_2NAN}, {`FP4_2NAN, `FP4_ANYF}: Y = `FP4_PINF;
    {`FP4_PINF, `FP4_NINF}, {`FP4_NINF, `FP4_PINF}: Y = `FP4_PINF;
    {`FP4_ANYF, `FP4_PINF}, {`FP4_PINF, `FP4_ANYF}: Y = `FP4_PNAN;
    default: Y = `FP4_PINF;
    endcase
end
endmodule

module bit_to_fp4(input A, output [3:0] Y);
assign Y = A ? `FP4_PNAN : `FP4_PINF;
endmodule

module fp4_to_bit(input [3:0] A, output reg Y);
always begin
    casez (A)
    `FP4_1NAN: Y = 1'b1;
    `FP4_2NAN: Y = 1'b1;
    default: Y = 1'b0;
    endcase
end
endmodule

`define FP5_PINF 5'b01100
`define FP5_NINF 5'b11100
`define FP5_PNAN 5'b01111
`define FP5_1NAN 5'b?1101
`define FP5_2NAN 5'b?111?
`define FP5_ANYF 5'b?????

module nan_fp5(
    input      [4:0] A,
    input      [4:0] B,
    output reg [4:0] Y
);

always begin
    casez ({A, B})
    {`FP5_ANYF, `FP5_1NAN}, {`FP5_1NAN, `FP5_ANYF}: Y = `FP5_PINF;
    {`FP5_ANYF, `FP5_2NAN}, {`FP5_2NAN, `FP5_ANYF}: Y = `FP5_PINF;
    {`FP5_PINF, `FP5_NINF}, {`FP5_NINF, `FP5_PINF}: Y = `FP5_PINF;
    {`FP5_ANYF, `FP5_PINF}, {`FP5_PINF, `FP5_ANYF}: Y = `FP5_PNAN;
    default: Y = `FP5_PINF;
    endcase
end
endmodule

module bit_to_fp5(input A, output [4:0] Y);
assign Y = A ? `FP5_PNAN : `FP5_PINF;
endmodule

module fp5_to_bit(input [4:0] A, output reg Y);
always begin
    casez (A)
    `FP5_1NAN: Y = 1'b1;
    `FP5_2NAN: Y = 1'b1;
    default: Y = 1'b0;
    endcase
end
endmodule