From 72d5489d0cbdc8f4b90c95ee66f947b65fd14936 Mon Sep 17 00:00:00 2001
From: Cassie Jones <code@witchoflight.com>
Date: Fri, 6 Mar 2020 23:24:38 +0100
Subject: [PATCH] Add "mult" examples

---
 example/mult.sv      | 41 +++++++++++++++++++++++++++++++++++++++++
 example/mult.ys      | 11 +++++++++++
 example/shift_reg.sv | 21 +++++++++++++++++++++
 3 files changed, 73 insertions(+)
 create mode 100644 example/mult.sv
 create mode 100644 example/mult.ys
 create mode 100644 example/shift_reg.sv

diff --git a/example/mult.sv b/example/mult.sv
new file mode 100644
index 0000000..f31e471
--- /dev/null
+++ b/example/mult.sv
@@ -0,0 +1,41 @@
+module mult #(
+    parameter WIDTH=32,
+    parameter STAGES=4
+) (
+    input clock,
+    input enable,
+    input [WIDTH-1:0] A,
+    input [WIDTH-1:0] B,
+    output valid,
+    output [WIDTH-1:0] O
+);
+
+// Retiming really is magical...
+wire [WIDTH-1:0] prod = A * B;
+shift_reg #(.WIDTH(1), .DEPTH(STAGES)) shr_valid (.clock(clock), .in(enable), .out(valid));
+shift_reg #(.WIDTH(WIDTH), .DEPTH(STAGES)) shr_mul (.clock(clock), .in(prod), .out(O));
+
+endmodule
+
+module shift_reg #(
+    parameter WIDTH=1,
+    parameter DEPTH=4
+) (
+    input clock,
+    input [WIDTH-1:0] in,
+    output [WIDTH-1:0] out
+);
+
+reg [WIDTH-1:0] state [DEPTH-1:0];
+assign out = state[DEPTH-1];
+
+integer i;
+always @(posedge clock) begin
+    state[0] <= in;
+    for (i = 1; i < DEPTH; i=i+1) begin
+        state[i] <= state[i-1];
+    end
+end
+
+endmodule
+
diff --git a/example/mult.ys b/example/mult.ys
new file mode 100644
index 0000000..df437eb
--- /dev/null
+++ b/example/mult.ys
@@ -0,0 +1,11 @@
+plugin -i nangate
+read_verilog -sv example/mult.sv
+# read_verilog -sv example/shift_reg.sv
+chparam -set WIDTH 16 -set STAGES 4 mult
+synth -flatten -top mult
+abc -g NAND -dff -D 1
+synth_nan -top mult
+synth_ice40 -noflatten -top mult
+flatten
+write_blif -gates -attr -param mult.blif
+stat
diff --git a/example/shift_reg.sv b/example/shift_reg.sv
new file mode 100644
index 0000000..3058740
--- /dev/null
+++ b/example/shift_reg.sv
@@ -0,0 +1,21 @@
+module shift_reg #(
+    parameter WIDTH=1,
+    parameter DEPTH=4
+) (
+    input clock,
+    input [WIDTH-1:0] in,
+    output [WIDTH-1:0] out
+);
+
+reg [WIDTH-1:0] state [DEPTH-1:0];
+assign out = state[DEPTH-1];
+
+integer i;
+always @(posedge clock) begin
+    state[0] <= in;
+    for (i = 1; i < DEPTH; i=i+1) begin
+        state[i] <= state[i-1];
+    end
+end
+
+endmodule
-- 
2.43.2