Begin implementing CPU with fetching and decoding

Begin implementing CPU with fetching and decoding

This starts an nMigen hardware implementation of the Jade Rose
processor. This is a large-scale, mostly untested implementation, which
is structured around a multi-cycle decode with an 8-bit memory bus. In
the first cycle, the instruction is fetched, in the second cycle, it's
either executed or the second byte of the instruction is fetched. Most
of the implementation so far is just the decode switch block.