Begin implementing CPU with fetching and decoding
authorCassie Jones <code@witchoflight.com>
Mon, 3 Feb 2020 06:27:14 +0000 (01:27 -0500)
committerCassie Jones <code@witchoflight.com>
Mon, 3 Feb 2020 06:27:14 +0000 (01:27 -0500)
commit18113f6d0854c03abd46eb6a65cc70b1c90e31d3
tree7475bdf5d062901fe7c5c7895b30d49c44f96417
parent7693c4915b061bc6b5cbbae64f62c6cbcc1e29b5
Begin implementing CPU with fetching and decoding

This starts an nMigen hardware implementation of the Jade Rose
processor. This is a large-scale, mostly untested implementation, which
is structured around a multi-cycle decode with an 8-bit memory bus. In
the first cycle, the instruction is fetched, in the second cycle, it's
either executed or the second byte of the instruction is fetched. Most
of the implementation so far is just the decode switch block.
.gitignore [new file with mode: 0644]
hardware/core.py [new file with mode: 0644]
hardware/main.py [new file with mode: 0644]