- log("");
- log("This command synthesizes a design into NaN gates.");
- log("");
- log(" -nosynth <width>");
- log(" skip the pre-run synthesis step. Requires that the circuit");
- log(" has already been synthesized down to NAND and NOT gates.");
- log("");
- log(" -pre-flatten");
- log(" flatten duing the initial coarse synthesis");
- log("");
- log(" -retime");
- log(" do retiming in ABC");
- log("");
- log(" -top <module>");
- log(" use the specified module as top module (default='top')");
- log("");
- log(" -width <width>");
- log(" synthesize with a given floating-point with (default=3)");
- log("");
+ log("\n");
+ log("This command synthesizes a design into NaN gates.\n");
+ log("\n");
+ log(" -nosynth <width>\n");
+ log(" skip the pre-run synthesis step. Requires that the circuit\n");
+ log(" has already been synthesized down to NAND and NOT gates.\n");
+ log("\n");
+ log(" -pre-flatten\n");
+ log(" flatten duing the initial coarse synthesis\n");
+ log("\n");
+ log(" -retime\n");
+ log(" do retiming in ABC\n");
+ log("\n");
+ log(" -top <module>\n");
+ log(" use the specified module as top module (default='top')\n");
+ log("\n");
+ log(" -width <width>\n");
+ log(" synthesize with a given floating-point with (default=3)\n");
+ log("\n");