Cassie Jones [Fri, 6 Mar 2020 21:53:14 +0000 (22:53 +0100)]
Support multiple synthesis widths
The original NaN gates paper describes 3-bit and 4-bit floating point
formats. The original synthesis was hard-coded for 3-bit synthesis, but
technically 5-bit floats are the smallest legal floating point values.
Allowing for different synthesis provides opportunities to compare the
different results.
Cassie Jones [Fri, 6 Mar 2020 17:29:46 +0000 (18:29 +0100)]
Do NaN synthesis pattern matching via attributes
The previous implementation of NaN synthesis used matching on cell
types, which wouldn't scale with adding support for larger cell types.
Using attributes allows for simply adding the appropriate width
attributes and figuring things out from there.
Cassie Jones [Wed, 4 Mar 2020 22:43:51 +0000 (23:43 +0100)]
Add install, use the installed cell libs
The extension needs to load a cell library in order to tech-map things,
and that means having a Verilog file at a locatable path. The Yosys
built-ins put them in the <share>/yosys directory, and so we install
things there and load them from there for convenience.
Using a path +/<path> will be rewritten inside Yosys to load from
<share>/yosys/<path>. I add a nangate/ sub-directory for namespacing
purposes during the install, and load things from +/nangate/<file>.