Support multiple synthesis widths
[nan-gate] / techlib.sv
1 `define FP3_PINF 3'b010
2 `define FP3_NINF 3'b110
3 `define FP3_PNAN 3'b011
4 `define FP3_ANAN 3'b?11
5 `define FP3_ANYF 3'b???
6
7 // A NaN gate! Computes `Inf - max(x+y, -Inf)`.
8 // See http://tom7.org/nand/
9 module nan_fp3(
10 input [2:0] A,
11 input [2:0] B,
12 output reg [2:0] Y
13 );
14
15 always begin
16 casez ({A, B})
17 {`FP3_ANYF, `FP3_ANAN}, {`FP3_ANAN, `FP3_ANYF}: Y = `FP3_PINF;
18 {`FP3_PINF, `FP3_NINF}, {`FP3_NINF, `FP3_PINF}: Y = `FP3_PINF;
19 {`FP3_ANYF, `FP3_PINF}, {`FP3_PINF, `FP3_ANYF}: Y = `FP3_PNAN;
20 default: Y = `FP3_PINF;
21 endcase
22 end
23 endmodule
24
25 // Convert a bit into an fp3
26 module bit_to_fp3(input A, output [2:0] Y);
27 assign Y = A ? `FP3_PNAN : `FP3_PINF;
28 endmodule
29
30 // Convert an fp3 into a bit
31 module fp3_to_bit(input [2:0] A, output reg Y);
32 always begin
33 casez (A)
34 `FP3_ANAN: Y = 1'b1;
35 default: Y = 1'b0;
36 endcase
37 end
38 endmodule
39
40 `define FP4_PINF 4'b0100
41 `define FP4_NINF 4'b1100
42 `define FP4_PNAN 4'b0111
43 `define FP4_1NAN 4'b?101
44 `define FP4_2NAN 4'b?11?
45 `define FP4_ANYF 4'b????
46
47 module nan_fp4(
48 input [3:0] A,
49 input [3:0] B,
50 output reg [3:0] Y
51 );
52
53 always begin
54 casez ({A, B})
55 {`FP4_ANYF, `FP4_1NAN}, {`FP4_1NAN, `FP4_ANYF}: Y = `FP4_PINF;
56 {`FP4_ANYF, `FP4_2NAN}, {`FP4_2NAN, `FP4_ANYF}: Y = `FP4_PINF;
57 {`FP4_PINF, `FP4_NINF}, {`FP4_NINF, `FP4_PINF}: Y = `FP4_PINF;
58 {`FP4_ANYF, `FP4_PINF}, {`FP4_PINF, `FP4_ANYF}: Y = `FP4_PNAN;
59 default: Y = `FP4_PINF;
60 endcase
61 end
62 endmodule
63
64 module bit_to_fp4(input A, output [3:0] Y);
65 assign Y = A ? `FP4_PNAN : `FP4_PINF;
66 endmodule
67
68 module fp4_to_bit(input [3:0] A, output reg Y);
69 always begin
70 casez (A)
71 `FP4_1NAN: Y = 1'b1;
72 `FP4_2NAN: Y = 1'b1;
73 default: Y = 1'b0;
74 endcase
75 end
76 endmodule
77
78 `define FP5_PINF 5'b01100
79 `define FP5_NINF 5'b11100
80 `define FP5_PNAN 5'b01111
81 `define FP5_1NAN 5'b?1101
82 `define FP5_2NAN 5'b?111?
83 `define FP5_ANYF 5'b?????
84
85 module nan_fp5(
86 input [4:0] A,
87 input [4:0] B,
88 output reg [4:0] Y
89 );
90
91 always begin
92 casez ({A, B})
93 {`FP5_ANYF, `FP5_1NAN}, {`FP5_1NAN, `FP5_ANYF}: Y = `FP5_PINF;
94 {`FP5_ANYF, `FP5_2NAN}, {`FP5_2NAN, `FP5_ANYF}: Y = `FP5_PINF;
95 {`FP5_PINF, `FP5_NINF}, {`FP5_NINF, `FP5_PINF}: Y = `FP5_PINF;
96 {`FP5_ANYF, `FP5_PINF}, {`FP5_PINF, `FP5_ANYF}: Y = `FP5_PNAN;
97 default: Y = `FP5_PINF;
98 endcase
99 end
100 endmodule
101
102 module bit_to_fp5(input A, output [4:0] Y);
103 assign Y = A ? `FP5_PNAN : `FP5_PINF;
104 endmodule
105
106 module fp5_to_bit(input [4:0] A, output reg Y);
107 always begin
108 casez (A)
109 `FP5_1NAN: Y = 1'b1;
110 `FP5_2NAN: Y = 1'b1;
111 default: Y = 1'b0;
112 endcase
113 end
114 endmodule