13 // Retiming really is magical...
14 wire [WIDTH-1:0] prod = A * B;
15 shift_reg #(.WIDTH(1), .DEPTH(STAGES)) shr_valid (.clock(clock), .in(enable), .out(valid));
16 shift_reg #(.WIDTH(WIDTH), .DEPTH(STAGES)) shr_mul (.clock(clock), .in(prod), .out(O));
26 output [WIDTH-1:0] out
29 reg [WIDTH-1:0] state [DEPTH-1:0];
30 assign out = state[DEPTH-1];
33 always @(posedge clock) begin
35 for (i = 1; i < DEPTH; i=i+1) begin
36 state[i] <= state[i-1];