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Add "mult" examples
[nan-gate] / example / mult.sv
1 module mult #(
2 parameter WIDTH=32,
3 parameter STAGES=4
4 ) (
5 input clock,
6 input enable,
7 input [WIDTH-1:0] A,
8 input [WIDTH-1:0] B,
9 output valid,
10 output [WIDTH-1:0] O
11 );
12
13 // Retiming really is magical...
14 wire [WIDTH-1:0] prod = A * B;
15 shift_reg #(.WIDTH(1), .DEPTH(STAGES)) shr_valid (.clock(clock), .in(enable), .out(valid));
16 shift_reg #(.WIDTH(WIDTH), .DEPTH(STAGES)) shr_mul (.clock(clock), .in(prod), .out(O));
17
18 endmodule
19
20 module shift_reg #(
21 parameter WIDTH=1,
22 parameter DEPTH=4
23 ) (
24 input clock,
25 input [WIDTH-1:0] in,
26 output [WIDTH-1:0] out
27 );
28
29 reg [WIDTH-1:0] state [DEPTH-1:0];
30 assign out = state[DEPTH-1];
31
32 integer i;
33 always @(posedge clock) begin
34 state[0] <= in;
35 for (i = 1; i < DEPTH; i=i+1) begin
36 state[i] <= state[i-1];
37 end
38 end
39
40 endmodule
41