Add "mult" examples
[nan-gate] / example / shift_reg.sv
1 module shift_reg #(
2 parameter WIDTH=1,
3 parameter DEPTH=4
4 ) (
5 input clock,
6 input [WIDTH-1:0] in,
7 output [WIDTH-1:0] out
8 );
9
10 reg [WIDTH-1:0] state [DEPTH-1:0];
11 assign out = state[DEPTH-1];
12
13 integer i;
14 always @(posedge clock) begin
15 state[0] <= in;
16 for (i = 1; i < DEPTH; i=i+1) begin
17 state[i] <= state[i-1];
18 end
19 end
20
21 endmodule