4 Eight completely symmetric general-purpose registers (r0-7)
 
   5 Special registers: pc (16-bit address), it (accumulator), data1 (segment), data2 (segment), code (segment)
 
   9 0000_0000          TRAP (invalid)
 
  10      0001          NOPE "no operation" (with a more fun mnemonic)
 
  11      0010          PRNT print it (for debugging or toy programs)
 
  14      0110          CABA call absolute code[it], it <- return addr, code <- return segment
 
  15      0111          COFA call offset pc ± it, it <- return offset (-it + 1)
 
  17 0000_1ooo          ALU1 it <- {zero, lsl1, lsr1, asr1, incr, decr, comp, negt} it
 
  19 0001_0000          GET1 it <- data1
 
  22      0011               (reserved for another special register)
 
  27      1011               (reserved for another special register)
 
  30 0010_0aaa          GETR it <- it
 
  32    1_0aaa          SWAP ra <- it, it <- ra
 
  33    1_1aaa          ISLT "is less than", for testing overflow / carries: it <- (it < ra) ? 1 : 0
 
  35 01oo_oaaa          ALUR it <- it {addr, subr, andr, iorr, xorr, lslr, lsrr, asrr} ra
 
  37 100i_0aaa          LD1U it <- data1[ra], then ra += i
 
  38   0i_1aaa          ST1U data1[ra] <- it, then ra += i
 
  39   1i_0aaa          LD2U it <- data2[ra], then ra += i
 
  40   1i_1aaa          ST2U data2[ra] <- it, then ra += i
 
  42 110x_xaaa               (reserved w/ register)
 
  43 1110_xaaa               (reserved w/ register)
 
  45 1111_00oo iiiiiiii ALUI it <- it {andi, iori, xori, (see below)} i
 
  46      0011 0iiiiiii ADDI it <- it + i
 
  47      0011 10oooiii BITI it <- it {roli, lsli, lsri, asri, clri, insi, togi, exti} i
 
  48      0011 11iiiiii ADDI it <- it + (whole field, thus allowing many negative numbers)
 
  49      0100 iiiiiiii BEZI branch pc ± i if it == 0
 
  50      0101 iiiiiiii JOFI jump offset to pc ± i
 
  51      0110 iiiiiiii CABI call absolute code[i], it <- return addr, code <- return segment
 
  52      0111 iiiiiiii COFI call offset pc ± i, it <- return offset (-i + 2)
 
  53      10xx iiiiiiii      (reserved w/ immediate)
 
  54      110x iiiiiiii      (reserved w/ immediate)
 
  55      1110 iiiiiiii GETI it <- i
 
  56      1111 xxxxxxxx EXT1 extended encoding for "future-proofing"
 
  58 11 free no-argument encodings
 
  59 6 free register encodings - possibly load-then-decrement? possibly 16-bit ADD and SUB with register pairs?
 
  60 6 free immediate encodings
 
  62 Some dubiously "nice" properties:
 
  64 - 1111_xxxx takes immediate
 
  65 - Register instructions are all consecutive (0010_0aaa through 1110_1aaa)
 
  66 - No reg/imm ops, so data line can be the immediate
 
  67 - Two data segments, because I'm generous like that
 
  68 - get/set pairs consistently differentiated by bit 5
 
  69 - Future-proofing! Because that's definitely a thing that this set needs
 
  70 - The nicest instruction is "ADDR r5"
 
  71 - Near and far calls (okay, this is not nice)