jade-rose
19 months agoAdd the wait state to the state machine develop
Cassie Jones [Mon, 3 Feb 2020 07:27:35 +0000 (02:27 -0500)]
Add the wait state to the state machine

The implementation of the WAIT state currently constantly reads from
memory at the WAIT-ed address, resuming when a nonzero value comes back.
It might be better to have specific support for that in an interrupt
controller type of hardware which would send notifications when the
appropriate address changed.

19 months agoBegin implementing CPU with fetching and decoding
Cassie Jones [Mon, 3 Feb 2020 06:27:14 +0000 (01:27 -0500)]
Begin implementing CPU with fetching and decoding

This starts an nMigen hardware implementation of the Jade Rose
processor. This is a large-scale, mostly untested implementation, which
is structured around a multi-cycle decode with an 8-bit memory bus. In
the first cycle, the instruction is fetched, in the second cycle, it's
either executed or the second byte of the instruction is fetched. Most
of the implementation so far is just the decode switch block.

19 months agoUpdate ISA spec to v0.2.2
Cassie Jones [Mon, 3 Feb 2020 03:56:45 +0000 (22:56 -0500)]
Update ISA spec to v0.2.2

19 months agoAdd basic README.md
Cassie Jones [Fri, 31 Jan 2020 00:43:11 +0000 (19:43 -0500)]
Add basic README.md

20 months agoUpdate immediate format to literals
Cassie Jones [Fri, 17 Jan 2020 20:24:53 +0000 (15:24 -0500)]
Update immediate format to literals

Following discussion on twitter, this is changing to match Jordan's
implementation.

https://twitter.com/UINT_MIN/status/1218190029207613441

> FWIW I picked a different integer syntax than you (Swift/Rust-style
> 0x123, 0b123) [...]

20 months agoMake parser conform to v0.2.1
Cassie Jones [Fri, 17 Jan 2020 19:43:43 +0000 (14:43 -0500)]
Make parser conform to v0.2.1

20 months agoUpgrade spec to v0.2.1
Cassie Jones [Fri, 17 Jan 2020 19:42:14 +0000 (14:42 -0500)]
Upgrade spec to v0.2.1

20 months agoUpgrade toolchain to ISA v0.2
Cassie Jones [Fri, 17 Jan 2020 08:21:05 +0000 (03:21 -0500)]
Upgrade toolchain to ISA v0.2

20 months agoImprove assembler/disassembler errors
Cassie Jones [Fri, 17 Jan 2020 04:47:45 +0000 (23:47 -0500)]
Improve assembler/disassembler errors

20 months agoImplement wrappers for web
Cassie Jones [Wed, 15 Jan 2020 02:11:34 +0000 (21:11 -0500)]
Implement wrappers for web

20 months agoUpdate spec
Cassie Jones [Mon, 13 Jan 2020 15:42:28 +0000 (10:42 -0500)]
Update spec

20 months agoAdd disassembler, update spec
Cassie Jones [Mon, 13 Jan 2020 15:41:47 +0000 (10:41 -0500)]
Add disassembler, update spec

20 months agoAdd instruction formatter
Cassie Jones [Sun, 12 Jan 2020 00:35:23 +0000 (19:35 -0500)]
Add instruction formatter

20 months agoAdd support for binary, hex, and octal literals
Cassie Jones [Sat, 11 Jan 2020 23:29:53 +0000 (18:29 -0500)]
Add support for binary, hex, and octal literals

20 months agoAdd decoding with proptest round-trip test
Cassie Jones [Sat, 11 Jan 2020 22:31:19 +0000 (17:31 -0500)]
Add decoding with proptest round-trip test

20 months agoAdd a very basic assembler utility
Cassie Jones [Sat, 11 Jan 2020 12:20:21 +0000 (07:20 -0500)]
Add a very basic assembler utility

20 months agoAdd parser and encoder tests, fix a parser bug
Cassie Jones [Sat, 11 Jan 2020 11:57:34 +0000 (06:57 -0500)]
Add parser and encoder tests, fix a parser bug

We test the parser by parsing an instruction, and then encoding it back
to binary, printed nicely. The test cases are generated by looking at
the spec table.

The parser was incorrectly parsing LD2U as ST2U. Fixed.

20 months agoAdd an instruction parser
Cassie Jones [Sat, 11 Jan 2020 11:10:33 +0000 (06:10 -0500)]
Add an instruction parser

20 months agoAdd instruction encoder
Cassie Jones [Sat, 11 Jan 2020 08:52:38 +0000 (03:52 -0500)]
Add instruction encoder

20 months agoAdd Reg constructor
Cassie Jones [Sat, 11 Jan 2020 07:42:32 +0000 (02:42 -0500)]
Add Reg constructor

20 months agoAdd encode and decode traits
Cassie Jones [Sat, 11 Jan 2020 06:50:31 +0000 (01:50 -0500)]
Add encode and decode traits

20 months agoAdd instruction datatype
Cassie Jones [Sat, 11 Jan 2020 06:44:06 +0000 (01:44 -0500)]
Add instruction datatype

20 months agoAdd Jordan Rose's ISA spec
Cassie Jones [Sat, 11 Jan 2020 05:58:12 +0000 (00:58 -0500)]
Add Jordan Rose's ISA spec