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Add Reg constructor
[jade-rose] / isa.txt
1 ISA by Jordan Rose
2
3 Eight completely symmetric general-purpose registers (r0-7)
4 Special registers: pc, it (accumulator), data1 (segment), data2 (segment), code (segment)
5
6 7654_3210
7
8 0000_0000 TRAP (invalid)
9 0001
10 001x
11 0100 JABS jump absolute to code[it]
12 0101 CABS call absolute code[it], it <- return addr, code <- return segment
13 0110 JOFF jump pc ± it
14 0111 COFF call pc ± it, it <- return offset (-it + 1)
15
16 0000_1aaa SWAP a <- it, it <- a
17 1_0aaa GETR it <- a
18 1_1aaa SETR a <- it
19
20 0010_0000 GET1 it <- data1
21 0001 GET2 it <- data2
22 0010 GETC it <- code
23 0011 (reserved for another special register)
24 01xx
25 1000 SET1 data1 <- it
26 1001 SET2 data2 <- it
27 1010 SETC code <- it
28 1011 (reserved for another special register)
29 11xx
30
31 0011_0ooo ALU1 it <- {zero, lsl1, lsr1, asr1, incr, decr, comp, negt} it
32 1aaa ISLT "is less than", for testing overflow / carries: it <- (it < a) ? 1 : 0
33 01oo_oaaa ALUR it <- it {addr, subr, andr, iorr, xorr, lslr, lsrr, asrr} a
34
35 100i_0aaa LD1U it <- data1[a], then a += i
36 0i_1aaa ST1U it <- data1[a], then a -= i
37 1i_0aaa LD2U it <- data2[a], then a += i
38 1i_1aaa ST2U it <- data2[a], then a -= i
39
40 110x_xxxx
41 1110_xxxx
42
43 1111_00oo iiiiiiii ALUI it <- it {andi, iori, xori, (see below)} i
44 0011 0iiiiiii ALUI it <- it + i (ADDI)
45 0011 100ooiii ALUI it <- it {roli, lsli, lsri, asri} i
46 0011 101xxxxx (probably permanently unused, but you could cram in more small ALU ops?)
47 0011 11iiiiii ALUI it <- it + (whole field, thus allowing many negative numbers) (ADDI)
48 0100 iiiiiiii BEZI branch ±i if it == 0
49 0101 iiiiiiii (reserved branch; SUB2, BLTI is no faster than ISLT, BEZI)
50 0110 iiiiiiii JOFI jump to ±i
51 0111 iiiiiiii COFI call ±i, it <- return offset (-it + 2)
52 1xxx iiiiiiii (reserved w/ immediate)
53
54
55 Some dubiously "nice" properties:
56 - 0 is invalid
57 - 1111_xxxx takes immediate
58 - No reg/imm ops, so data line can be the immediate
59 - Two data segments, because I'm generous like that
60 - get/set pairs consistently differentiated by bit 5
61 - jump/call pairs differentiated by bit 0
62 - The nicest instruction is "ADDR r5"
63 - Near and far calls (okay, this is not nice)
64
65
66 # Half-adder it + r0
67 ADDR r0
68 SETR r1
69 ISLT r0
70 SWAP r1
71 # main result in it, carry in r1
72 # more work to make a full adder though
73
74 # Half-subtractor it - r0
75 SETR r1
76 ISLT r0
77 SWAP r1
78 SUBR r0
79 # main result in it, carry in r0
80 # more work to make a full subtracter