Cassie Jones [Mon, 3 Feb 2020 07:27:35 +0000 (02:27 -0500)]
Add the wait state to the state machine
The implementation of the WAIT state currently constantly reads from
memory at the WAIT-ed address, resuming when a nonzero value comes back.
It might be better to have specific support for that in an interrupt
controller type of hardware which would send notifications when the
appropriate address changed.
Cassie Jones [Mon, 3 Feb 2020 06:27:14 +0000 (01:27 -0500)]
Begin implementing CPU with fetching and decoding
This starts an nMigen hardware implementation of the Jade Rose
processor. This is a large-scale, mostly untested implementation, which
is structured around a multi-cycle decode with an 8-bit memory bus. In
the first cycle, the instruction is fetched, in the second cycle, it's
either executed or the second byte of the instruction is fetched. Most
of the implementation so far is just the decode switch block.
Cassie Jones [Sat, 11 Jan 2020 11:57:34 +0000 (06:57 -0500)]
Add parser and encoder tests, fix a parser bug
We test the parser by parsing an instruction, and then encoding it back
to binary, printed nicely. The test cases are generated by looking at
the spec table.
The parser was incorrectly parsing LD2U as ST2U. Fixed.