Update benchmark to match the yosys 4-bit counter
[minecraft-eda] / example / counter.sv
1 module counter #(parameter WIDTH=4) (
2 input clock,
3 input reset,
4 input enable,
5 output logic [WIDTH-1:0] count,
6 );
7
8 always_ff @(posedge clock) begin
9 if (reset) count <= 0;
10 else if (enable) count <= count + 1;
11 end
12
13 endmodule