descriptionElectronic design automation tools for Minecraft
last changeFri, 3 May 2019 19:31:51 +0000 (12:31 -0700)
readme

Minecraft Logic Synthesis Project

I had the terrible idea of synthesizing Verilog to redstone with yosys and nextpnr. Let's figure out how to do that!

shortlog
2019-05-03 Cassie JonesUpdate benchmark to match the yosys 4-bit counter develop
2019-04-29 Cassie JonesAdd romgen, a tool to generate ROMs for litho
2019-04-29 Cassie JonesAdd "lithography" binary that places blocks
2019-04-27 Cassie JonesGenerate the libery with a script
2019-04-27 Cassie JonesAdd a rust program to put designs into minecraft
2019-04-27 Cassie JonesAdd the beginning of a redstone liberty file
2019-04-27 Cassie JonesAdd example counter
2019-04-27 Cassie JonesAdd README and an example verilog file
heads
2 years ago genlib
2 years ago develop